Dr. D.C. Kiran

Associate Professor, School of
Computational and Data Sciences
Former Associate Professor, PES University
Ph.D. in Computer Engineering, BITS-Pilani
B.E. (Computer Science & Engineering)
M.E. (Computer Science & Engineering)
Masters in Business Law (NLSIU)

Selected Publications

• D C Kiran, T S B Sudarshan and S Gurunarayanan., "Variable Partitioning to Solve Dual Bank Register Allocation for Network Processor", National Conference on High Performance Computing, AITS, Rajkot, Gujarat (India), November 2008, pp (Best Paper Presentation Award).
• D.C. Kiran, S. Gurunarayanan, and J.P.Misra, "Taming Compiler to Work with Multicore Processors". IEEE Conference on Process Automation, Control and Computing. 2011.
• D.C.Kiran, B. Radheshyam. S. Gurunarayanan, and J.P.Misra, "Compiler Assisted Dynamic Scheduling for Multicore Processors". IEEE Conference on Process Automation, Control and Computing. 2011.
• D.C. Kiran, S. Gurunarayanan, J.P.Misra and Faizan Khaliq, "An Efficient Method to Compute Static Single Assignment Form for Multicore Architecture". In 1st IEEE International Conference on Recent Advances in Information Technology, pp. 776-789, March 2012.
• D.C. Kiran, S. Gurunarayanan, and J.P.Misra, "Compiler Driven Inter Block Parallelism for Multicore Processors". In 6th International Conference on Information Processing, published in the Communications in Computer and Information Science (CCIS), Springer-Verlag, August 2012.
• D.C. Kiran, S. Gurunarayanan, Faizan Khaliq, and Abhijeet Nawal, "Compiler Efficient and Power Aware Instruction Level Parallelism for Multicore Architectures". In The International Eco-friendly Computing and Communication Systems, published in the Communications in Computer and Information Science (CCIS), Springer- Verlag, pp.9-17 August 2012.
• D.C. Kiran, S. Gurunarayanan, J.P.Misra, and D.Yashas "Integrated Scheduling and Register Allocation For Multicore Architecture". In IEEE Conference on Parallel Computing Technologies PARCOMPTECH-2013, Organized by C-DAC in IISC Bangalore, February 2013.
• Munish Bhathia, D.C.Kiran, S Gurunarayanan, and J.P.Misra, "Fine Grain Thread Scheduling on Multicore Processors: Cores With Multiple Functional Units". ACM Compute. Aug 2013.
• D. C. Kiran, S. Gurunarayanan, Janardan Prasad Misra, and Abhijeet Nawal, “Global Scheduling Heuristics for Multicore Architecture,” Scientific Programming, vol. 2015, Article ID 860891, 12 pages, 2015
• D.C. Kiran, S. Gurunarayanan, J.P.Misra & Munish Bhathia "Register Allocation for Fine Grained Threads on Multicore Processors". Journal of King Saud University - Computer and Information Sciences, Elsevier
• D.C. Kiran "Compiler Support and Optimization for Multicore Processors" Ph.D Forum -organized in conjunction with ICDCN 2013 at Tata Institute of Fundamental Research, Mumbai, January 3-6, 2013.