Dr. D.C. Kiran | Vidyashilp University Faculty

Dr. D.C. Kiran

Associate Professor, School of
Computational and Data Sciences
Former Associate Professor, PES University
Ph.D. in Computer Engineering, BITS-Pilani
B.E. (Computer Science & Engineering)
M.E. (Computer Science & Engineering)
Masters in Business Law (NLSIU)
Mail| Dr. D.C. Kiran Vidyashilp University Faculty


Biography
Professional Education
Teaching Courses
Research Interests
Selected Publications
Research Projects
Undertaken
Research Supervisor to
Biography

Dr. Kiran D C is a passionate teacher, administrator, & researcher. He has more than two (02) decades of teaching, research, and administrative experience. Being the founding member of two green field Universities, Dr Kiran has served as Registrar (i/c), Chief Warden, Member of Research Committee, and was instrumental in setting up State of art lab in Presidency University and Vidyashilp University.

Dr. Kiran has also been serving as a Mentor of Change with Atal Innovation Mission, NITI Aayog and Advisor for Makonis Software Ltd. Some of his recent consulting engagements have encompassed, building low-cost cluster for academic experiments, IoT, VR & AR based projects.

He has served as a nucleus member of Work Integrated Learning Programming Division (off-campus program of BITS-Pilani) which offers a degree for employed professionals. He has taught working professionals at Wipro Technologies, L&T, CISCO and Hindustan Zinc Ltd. His teaching has been well appreciated, accepted and have always produced an excellent result.

Dr. Kiran passion for education has motivated him to be systematic and analytical throughout his long career in the education field. He believes that skill centered learning is a crucial part of education and should be given greater importance in educational institutions.

Professional Education
  • PhD (BITS-PILANI); Computer Science - 2015
  • Master of Business Law (NLSIU) - 2022
  • ME (Anna University) Computer Science and Engineering - 2004
  • BE (VTU) Computer Science and Engineering - 2002

Teaching Courses
  • Computational Thinking
  • Introduction to Digital World
  • Data Structure
  • Database Management
  • Theoretical Computer Science
  • Microprocessor and Computer Architecture
  • Digital Design
  • Parallel Computing
  • Secure C Programming
  • R Programming
  • Programming Language and Compiler Design
  • Formal Languages and Finite Automata
  • Operating System

Research Interests
  • High Performance Computing
  • Compiler Optimization
  • Computational Thinking
  • Robots for AI application

Selected Publications
  • D C Kiran, T S B Sudarshan and S Gurunarayanan., "Variable Partitioning to Solve Dual Bank Register Allocation for Network Processor", National Conference on High Performance Computing, AITS, Rajkot, Gujarat (India), November 2008, pp (Best Paper Presentation Award).
  • D.C. Kiran, S. Gurunarayanan, and J.P.Misra, "Taming Compiler to Work with Multicore Processors". IEEE Conference on Process Automation, Control and Computing. 2011.
  • D.C.Kiran, B. Radheshyam. S. Gurunarayanan, and J.P.Misra, "Compiler Assisted Dynamic Scheduling for Multicore Processors". IEEE Conference on Process Automation, Control and Computing. 2011.
  • D.C. Kiran, S. Gurunarayanan, J.P.Misra and Faizan Khaliq, "An Efficient Method to Compute Static Single Assignment Form for Multicore Architecture". In 1st IEEE International Conference on Recent Advances in Information Technology, pp. 776-789, March 2012.
  • D.C. Kiran, S. Gurunarayanan, and J.P.Misra, "Compiler Driven Inter Block Parallelism for Multicore Processors". In 6th International Conference on Information Processing, published in the Communications in Computer and Information Science (CCIS), Springer-Verlag, August 2012.
  • D.C. Kiran, S. Gurunarayanan, Faizan Khaliq, and Abhijeet Nawal, "Compiler Efficient and Power Aware Instruction Level Parallelism for Multicore Architectures". In The International Eco-friendly Computing and Communication Systems, published in the Communications in Computer and Information Science (CCIS), Springer- Verlag, pp.9-17 August 2012.
  • D.C. Kiran, S. Gurunarayanan, J.P.Misra, and D.Yashas "Integrated Scheduling and Register Allocation For Multicore Architecture". In IEEE Conference on Parallel Computing Technologies PARCOMPTECH-2013, Organized by C-DAC in IISC Bangalore, February 2013.
  • Munish Bhathia, D.C.Kiran, S Gurunarayanan, and J.P.Misra, "Fine Grain Thread Scheduling on Multicore Processors: Cores With Multiple Functional Units". ACM Compute. Aug 2013.
  • D. C. Kiran, S. Gurunarayanan, Janardan Prasad Misra, and Abhijeet Nawal, “Global Scheduling Heuristics for Multicore Architecture,” Scientific Programming, vol. 2015, Article ID 860891, 12 pages, 2015
  • D.C. Kiran, S. Gurunarayanan, J.P.Misra & Munish Bhathia "Register Allocation for Fine Grained Threads on Multicore Processors". Journal of King Saud University - Computer and Information Sciences, Elsevier
  • D.C. Kiran "Compiler Support and Optimization for Multicore Processors" Ph.D Forum -organized in conjunction with ICDCN 2013 at Tata Institute of Fundamental Research, Mumbai, January 3-6, 2013.

Research Projects Undertaken
  • Building low-cost cluster for academic experiments
  • Applying the concept of Computational Thinking in teaching K-12 students in Indian Scenario.

Research Supervisor to

Mr Chethan Prabhu

Dr. Kiran D C is a passionate teacher, administrator, & researcher. He has more than two (02) decades of teaching, research, and administrative experience. Being the founding member of two green field Universities, Dr Kiran has served as Registrar (i/c), Chief Warden, Member of Research Committee, and was instrumental in setting up State of art lab in Presidency University and Vidyashilp University.

Dr. Kiran has also been serving as a Mentor of Change with Atal Innovation Mission, NITI Aayog and Advisor for Makonis Software Ltd. Some of his recent consulting engagements have encompassed, building low-cost cluster for academic experiments, IoT, VR & AR based projects.

He has served as a nucleus member of Work Integrated Learning Programming Division (off-campus program of BITS-Pilani) which offers a degree for employed professionals. He has taught working professionals at Wipro Technologies, L&T, CISCO and Hindustan Zinc Ltd. His teaching has been well appreciated, accepted and have always produced an excellent result.

Dr. Kiran passion for education has motivated him to be systematic and analytical throughout his long career in the education field. He believes that skill centered learning is a crucial part of education and should be given greater importance in educational institutions.

  • PhD (BITS-PILANI); Computer Science - 2015
  • Master of Business Law (NLSIU) - 2022
  • ME (Anna University) Computer Science and Engineering - 2004
  • BE (VTU) Computer Science and Engineering - 2002
  • Computational Thinking
  • Introduction to Digital World
  • Data Structure
  • Database Management
  • Theoretical Computer Science
  • Microprocessor and Computer Architecture
  • Digital Design
  • Parallel Computing
  • Secure C Programming
  • R Programming
  • Programming Language and Compiler Design
  • Formal Languages and Finite Automata
  • Operating System
  • High Performance Computing
  • Compiler Optimization
  • Computational Thinking
  • Robots for AI application
  • D C Kiran, T S B Sudarshan and S Gurunarayanan., "Variable Partitioning to Solve Dual Bank Register Allocation for Network Processor", National Conference on High Performance Computing, AITS, Rajkot, Gujarat (India), November 2008, pp (Best Paper Presentation Award).
  • D.C. Kiran, S. Gurunarayanan, and J.P.Misra, "Taming Compiler to Work with Multicore Processors". IEEE Conference on Process Automation, Control and Computing. 2011.
  • D.C.Kiran, B. Radheshyam. S. Gurunarayanan, and J.P.Misra, "Compiler Assisted Dynamic Scheduling for Multicore Processors". IEEE Conference on Process Automation, Control and Computing. 2011.
  • D.C. Kiran, S. Gurunarayanan, J.P.Misra and Faizan Khaliq, "An Efficient Method to Compute Static Single Assignment Form for Multicore Architecture". In 1st IEEE International Conference on Recent Advances in Information Technology, pp. 776-789, March 2012.
  • D.C. Kiran, S. Gurunarayanan, and J.P.Misra, "Compiler Driven Inter Block Parallelism for Multicore Processors". In 6th International Conference on Information Processing, published in the Communications in Computer and Information Science (CCIS), Springer-Verlag, August 2012.
  • D.C. Kiran, S. Gurunarayanan, Faizan Khaliq, and Abhijeet Nawal, "Compiler Efficient and Power Aware Instruction Level Parallelism for Multicore Architectures". In The International Eco-friendly Computing and Communication Systems, published in the Communications in Computer and Information Science (CCIS), Springer- Verlag, pp.9-17 August 2012.
  • D.C. Kiran, S. Gurunarayanan, J.P.Misra, and D.Yashas "Integrated Scheduling and Register Allocation For Multicore Architecture". In IEEE Conference on Parallel Computing Technologies PARCOMPTECH-2013, Organized by C-DAC in IISC Bangalore, February 2013.
  • Munish Bhathia, D.C.Kiran, S Gurunarayanan, and J.P.Misra, "Fine Grain Thread Scheduling on Multicore Processors: Cores With Multiple Functional Units". ACM Compute. Aug 2013.
  • D. C. Kiran, S. Gurunarayanan, Janardan Prasad Misra, and Abhijeet Nawal, “Global Scheduling Heuristics for Multicore Architecture,” Scientific Programming, vol. 2015, Article ID 860891, 12 pages, 2015
  • D.C. Kiran, S. Gurunarayanan, J.P.Misra & Munish Bhathia "Register Allocation for Fine Grained Threads on Multicore Processors". Journal of King Saud University - Computer and Information Sciences, Elsevier
  • D.C. Kiran "Compiler Support and Optimization for Multicore Processors" Ph.D Forum -organized in conjunction with ICDCN 2013 at Tata Institute of Fundamental Research, Mumbai, January 3-6, 2013.
  • Building low-cost cluster for academic experiments
  • Applying the concept of Computational Thinking in teaching K-12 students in Indian Scenario.

Mr Chethan Prabhu

Study at VU